1. Field of the Invention
The invention disclosed herein relates to systems for transferring digital data and more particularly to systems which generate and check parity while transferring data.
2. Description of the Prior Art
Parity generation and checking has long been used in the computer arts to confirm the integrity of a word of data. When a word of data is transmitted from one device to another, the sending device also generates a parity value for the word and transmits a parity signal representing the parity value. The value of the parity signal indicates whether there was an even or odd number of bits in the word with the value "1". The receiving device receives the word and generates its own parity value from the received word; if that parity value is different from the one represented by the parity signal for the word the received word has an odd number of "1" bits where the transmitted word had an even number or vice-versa. Consequently, by checking parity, the receiving device can detect any change in the value of the transmitted data which involves an odd number of bits.
A difficulty with parity checking in the prior art has been upgrading from systems which did not check parity to systems that did. Even though a bus had provisions for parity checking, devices which checked parity could not do so if other devices were attached to the bus which did not perform parity checking. Consequently, no gradual upgrading of devices to perform parity checking was possible. Once a decision was made to use a bus which provided for parity checking, all devices which were to be attached thereto had to be upgraded to perform parity checking at the same time.
A further difficulty with parity checking in the prior art has been that the generation of a parity value requires time, and consequently, devices which performed parity checking required longer bus cycles than devices which did not. The addition of parity checking thus slowed the whole system down. Moreover, the requirement for bus cycles longer than those for devices that did not parity check further aggravated the problem of connecting both types of devices to the same synchronous bus.
Another difficulty with parity checking has been that the transmitting and receiving devices have known that there was a parity error, but there has been no simple mechanism for determining independently of the transmitting and receiving devices that a parity error had occurred during the transmission. It is an object of the apparatus and methods disclosed in the present application to solve these problems and others as well.